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Integrated Circuit Systems, Inc.
ICS950602
Programmable Timing Control HubTM for PII/IIITM
Recommended Application: VIA Mobile PL133T and PLE133T Chipsets. Output Features: * 2 - CPU clocks @ 2.5V * 1 - Pairs of differential CPU clocks @ 3.3V * 7 - PCI including 1 free running @ 3.3V * 7 - SDRAM @ 3.3V * 1 - 48MHz @ 3.3V fixed * 1 - 24_48MHz selectable @ 3.3V * 2 - REF @ 3.3V, 14.318MHz Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz crystal. Key Specifications: * CPU Output Jitter <200ps * CPU Output Skew <175ps * PCI to PCI Output Skew <500ps
GND *FS2/REF1 REF0 Vtt_PWRGD# VDDREF GND X1 X2 VDDPCI *FS4/PCICLK_F *FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 SDRAM_IN *CPU_STOP# *PCI_STOP# *PD# **MULTISEL GND SDATA
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 CPUCLK0 CPUCLK1 VDDCPU_2.5 VDDCPU_3.3 CPUCLKT CPUCLKC GND RESET# I REF SDRAM6 GND SDRAM0 SDRAM1 VDDSDRAM SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDSDRAM AVDD48 48MHz/FS0* 24_48MHz/FS1* SCLK
48-Pin SSOP & TSSOP
* Internal Pull-up resistor of 120K to VDD ** these inputs have 120K internal pull-down to GND
Block Diagram
Host Swing Select Functions
MULTISEL0 0 1 Board Target Trace/Term Z 50 ohms 50 ohms Reference R, Iref = VDD/(3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 4* I REF Ioh = 6* I REF Voh @ Z 1.0V @ 50 0.7V @ 50
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ICS950602
Integrated Circuit Systems, Inc.
ICS950602
General Description
The ICS950602 is a single chip clock solution for VIA Mobile PL133T and PLE133T chipsets. It provides all necessary clock signals for such a system. The ICS950602 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With all these programmable features, ICS' TCH makes motherboard testing, tuning and improvement very simple.
Pin Description
PIN NUMBER 1, 6, 12, 23, 32, 38, 42, 5, 9, 29, 35 2 3 4 7 8 10 PCICLK_F 11 17, 16, 15, 14, 13 18 19 20 21 22 24 25 26 FS3 PCICLK0 PCICLK (5:1) SDRAM_IN CPU_STOP# PCI_STOP# PD# MULTSEL SDATA SCLK FS1 48_24MHz FS0 27 48MHz 28 30, 31, 33, 34, 36, 37, 39 40 41 43 44 45 46 47, 48
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PIN NAME GND VDD FS2 REF1 REF0 Vtt_PWRGD# X1 X2 FS4
TYPE PWR PWR IN OUT OUT IN IN OUT IN OUT IN OUT OUT IN IN IN IN IN I/O IN IN OUT IN OUT PWR OUT OUT OUT OUT OUT PWR PWR OUT Ground pins for 3.3V supply 3 . 3 V p ow e r s u p p l y
DESCRIPTION
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V, 14.318MHz reference clock output. 3.3V, 14.318MHz reference clock output. This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0) are valid and are ready to be sampled (active low) Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF) L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V PCI clock output L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V PCI clock output 3.3V PCI clock outputs SDRAM buffer input pin. Stops all CPUCLKs clocks at logic 0 level, when input low Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, w h e n i n p u t l ow Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled and the VCO and the cr ystal are s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. 3.3V LVTTL input for selecting the current multiplier for CPU outputs. Data pin for I2C circuitry 5V tolerant Clock pin for I2C circuitry 5V tolerant L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . Selectable 48 or 24MHz output L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V Fixed 48MHz clock output. 3.3V analog power supply for 48 or 24MHz outputs. SDRAM clock outputs. This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. Real time system reset signal for frequency value or watchdog timer timeout. This signal is active low. "Complementary" clock of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clock of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 3.3V power for CPU differential clocks. 2.5V power for CPU clocks. CPU clock outputs.
AVDD48 SDRAM (5:0, 6) I REF RESET# CPUCLKC CPUCLKT VDDCPU_3.3 VDDCPU_2.5 CPUCLK (1:0)
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Integrated Circuit Systems, Inc.
ICS950602
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
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ICS950602
Byte 0: Functionality and frequency select register (Default=0)
Bit Description Bit2 Bit1 Bit6 Bit5 Bit4 CPUCLK PCICLK MHz MHz FS4 FS3 FS2 FS1 FS0 Spread % PWD
Bit (2:1,6:4)
Bit 3 Bit 0 Bit 7
0 0 0 0 0 200.00 33.30 +/-0.25% center spread 0 0 0 0 1 190.00 38.00 +/-0.25% center spread 0 0 0 1 0 180.00 36.00 +/-0.25% center spread 0 0 0 1 1 170.00 34.00 +/-0.25% center spread 0 0 1 0 0 166.00 33.20 +/-0.25% center spread 0 0 1 0 1 160.00 32.00 +/-0.25% center spread 0 0 1 1 0 150.00 37.50 +/-0.25% center spread 0 0 1 1 1 145.00 36.30 +/-0.25% center spread 0 1 0 0 0 140.00 35.00 +/-0.25% center spread 0 1 0 0 1 136.00 34.00 +/-0.25% center spread 0 1 0 1 0 130.00 32.50 +/-0.25% center spread 0 1 0 1 1 124.00 31.00 +/-0.25% center spread 0 1 1 0 0 67.20 33.60 +/-0.25% center spread 0 1 1 0 1 100.90 33.63 +/-0.25% center spread 0 1 1 1 0 118.00 39.30 +/-0.25% center spread 0 1 1 1 1 134.40 33.60 +/-0.25% center spread 1 0 0 0 0 67.00 33.50 +/-0.25% center spread 1 0 0 0 1 100.50 33.50 +/-0.25% center spread 1 0 0 1 0 115.00 38.30 +/-0.25% center spread 1 0 0 1 1 133.90 33.47 +/-0.25% center spread 1 0 1 0 0 66.80 33.40 +/-0.25% center spread 1 0 1 0 1 100.20 33.40 +/-0.25% center spread 1 0 1 1 0 110.00 36.70 +/-0.25% center spread 1 0 1 1 1 133.60 33.40 +/-0.25% center spread 1 1 0 0 0 105.00 35.00 +/-0.25% center spread 1 1 0 0 1 90.00 30.00 +/-0.25% center spread 1 1 0 1 0 85.00 28.30 +/-0.25% center spread 1 1 0 1 1 78.00 39.00 +/-0.25% center spread 1 1 1 0 0 66.60 33.30 +/-0.25% center spread 1 1 1 0 1 100.00 33.30 0 to -0.5% down spread 1 1 1 1 0 75.00 37.50 +/-0.25% center spread 1 1 1 1 1 133.30 33.30 0 to -0.5% down spread 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2,7:4 0 - Normal 1 - Spread spectrum enable 0 - Watch dog safe frequency will be selected by latch inputs 1 - Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Note 1
0 0 0
Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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Integrated Circuit Systems, Inc.
ICS950602
Byte 1: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 48 47 44, 43
PWD X X X X X 1 1 1
Description FS4 Read back FS3 Read back FS2 Read back FS1 Read back FS0 Read back CPUCLK0 CPUCLK1 CPUCLKT, CPUCLKC
Byte 2: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# 39 10 17 16 15 14 13 11
PWD 1 1 1 1 1 1 1 1
Description SDRAM6 PCICLK_F PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Byte 3: Output Control Register (1 = enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin# 27 26 31, 30 34, 33 37, 36 PWD 0 0 1 1 0 1 1 1 Description RESET gear shift detect 1 = Enable, 0 = Disable S E L24_48: 0 = 24, 1 = 48 48MHz 24_48MHz Reserved SDRAM (4:5) SDRAM (2:3) SDRAM (0:1)
Byte 4: Output Control Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Pin# -
PWD X X X X X X X X
Description MULTSEL Read back Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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Integrated Circuit Systems, Inc.
ICS950602
Byte 5: Output Control Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Pin# 2 3 PWD 0 0 0 0 0 0 1 1 Description Reserved Reserved Reserved CPUCLK0 Free running control, 0 = Not free running 1 = Free running CPUCLK1 Free running control, 0 = Not free running 1 = Free running CPUCLKT/C Free running control, 0 = Not free running 1 = Free running REF1 REF0
Byte 6: Reserved Register (1 = enable, 0 = disable)
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Pin# -
PWD 0 0 0 0 0 0 0 0
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 7: Byte Count Read Back Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0 Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0 PWD Description 0 0 0 0 Default Byte count read back is 15 Byte. 1 1 1 1
Byte 8: Vendor ID Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Revision ID Bit3 Revision ID Bit2 Revision ID Bit1 Revision ID Bit0 Vendor ID Bit3 Vendor ID Bit2 Vendor ID Bit1 Vendor ID Bit0
PWD X X X X 0 0 0 1
Description Revision ID values will be based on individual device's revision (Reserved) (Reserved) (Reserved) (Reserved)
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ICS950602
Byte 9: Watchdog Timer Count Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD Description 0 0 0 The decimal representation of these 8 bits correspond to X * 1 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 0 16 * 290ms = 4.64 seconds. 0 0 0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Program Enable WD Enable WD Alarm S F4 S F3 S F2 S F1 S F0
PWD 0 0 0 1 1 1 1 1
Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2C programing. Watchdog Enable bit. This bit will over write WDEN latched value. 0 = disable, 1 = Enable. Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD Description X X X The decimal representation of Ndiv (8:0) correspond to the X VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11. X X X X
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Integrated Circuit Systems, Inc.
ICS950602
Byte 13: Spread Spectrum Control Register
Bit Bi t 7 Bi t 6 Bi t 5 Bi t 4 Bi t 3 Bi t 2 Bi t 1 Bi t 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD X X X X X X X X
Description The Spread Spectrum will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use ICS software for spread programming. Default power on is latched FS divider.
Byte 14: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
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Integrated Circuit Systems, Inc.
ICS950602
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Operating Supply Current Powerdown Current Input Frequency Pin Inductance Input Capacitance Transition time
1 1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX Ttrans Ts TSTAB Logic Inputs VIN = VDD
CONDITIONS
MIN 2 VSS - 0.3 -5 -5 -200
TYP
MAX VDD + 0.3 0.8 5
UNITS V V mA mA
VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 67 MHz CL =Full load, SDRAM not running IREF = 2.32 mA IREF = 5 mA VDD = 3.3 V
100 144 22 14.32 280 20 37 7 5 6 27 45 3 3 3 1 1 10 10
mA mA MHz nH pF pF pF ms ms ms ns ns
Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency
Settling time 1 Clk Stabilization Delay
1 1
tPZH,tPZL Output enable delay (all outputs) tPHZ,tPLZ Output disable delay (all outputs)
Guaranteed by design, not 100% tested in production.
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ICS950602
Electrical Characteristics - CPUCLK(T,C)
TA = 0 - 70C; VDD=3.3V +/-5%; loads from Intel CK408B spec, Rev 1.1 (unless otherwise specified) PARAMETER Current Source Output Impedance Output High Voltage Output High Current Rise Time Fall Time Voltage
1 1 1
SYMBOL ZO2A VOH2A IOH32A tr2A tf2A V2A dt2A
1
CONDITIONS VO = Vx VR = 475 +1%; IREF = 2.32 mA; IOH = 6*IREF VOL = -0.35V, VOH = 0.35V VOH = 0.35V, VOL = -0.35V Rs = 33.2, Rp = 63.4 to gnd, RT-C = 475 VT = crossing point VT (CPU) = crossing point, VT (PCI) = 1.25 V VT (CPU) = crossing point, VT (PCI) = 1.5 V VT = crossing point CPU,SD = 100MHz 100 MHz 133 MHz
MIN 3000
TYP
MAX
UNITS
0.71 -13.92 175 175 510 45 220 230 700 49 250 170 2 3.2 50
1.2 467 467 900 55 300 200 4 200
V mA ps ps mV % ps ns ps
Differential Crossover
1 1
Duty Cycle
Skew, CPUT,C to CPU Skew, CPUT,C to PCI Jitter, Cycle to cycle
1 1
tsk2A tsk2A1 tjcyc-cyc2A
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK(1:0)
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Impedance1 Output Impedance1 Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
SYMBOL RDSP2B RDSN2B VOH2B VOL2B IOH2B IOL2B tr2B tf2B dt2B
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@MIN = 1.0 V, VOH@MAX = 2.375 V VOL@MIN = 1.2 V, VOL@MIN = 0.3 V VOL = 0.4V, VOH = 2.0V VOH = 2.0V VOL = 0.4V VT = 50% VT = 1.25 V VT (CPU) = 1.25 V, VT (PCI) = 1.5 V VT = 1.25V CPU,SD = 100MHz CPU,SD = 133 MHz 100MHz 133 MHz
MIN 13.5 13.5 2 -27 27 0.4 45
TYP
MAX 45 45 0.4 27 30
UNITS V V ns % ps ns ps
0.7 0.8 50 54 60 3.2 140 100 220
1.6 55 175 4 250 250 275
Duty Cycle
Skew, CPU to CPU Skew, CPU to PCI
1
tsk2B tsk2B1
1
2
Jitter, Cycle to cycle
1
1
tjcyc-cyc2B
CPU = 100, SD = 133 MHz Guaranteed by design, not 100% tested in production.
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ICS950602
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL Output Frequency FO1 Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew
1
CONDITIONS
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33.33
MAX 55 0.55 -33 38
UNITS MHz V V mA mA ns ns % ps ps
RDSP11 VO = VDD*(0.5) VOH11 VOL11 I OH11 I OL11 tr11 tf11 dt11 tsk11
1
IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, V OL @MAX = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
2.4 2.25 53 220 300
2.5 2.5 55 500 450
Jitter,cycle to cycle tjcyc-cyc
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz, 24_48MHz
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN 1 Output Frequency FO3 1 Output Impedance RDSP3 VO = VDD*(0.5) 12 1 IOH = -1 mA 2.4 Output High Voltage VOH3 1 Output Low Voltage VOL3 IOL = 1 mA 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 Output High Current IOH3 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 Output Low Current IOL3 1 Rise Time tr3A VOL = 0.4 V, VOH = 2.4 V 1 1 Fall Time tf3B VOH = 2.4 V, VOL = 0.4 V 1 1 VT = 1.5 V 45 Duty Cycle dt3A 1 tjcyc-cyc3 VT = 1.5 V Jitter, cycle-to-cycle
1
TYP 48
MAX 55 0.55 -23 27 2 2 55 350
1.1 1.25 52 200
UNITS MHz V V mA mA ns ns % ps
Guaranteed by design, not 100% tested in production.
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ICS950602
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Impedance Output Impedance
1 1
SYMBOL RDSP5 RDSN5 VOH5 VOL5 IOH5 IOL5 tr5 tf5
1
CONDITIONS Vo=VDD*(0.5) Vo=VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH@MIN = 2 V VOH@MAX = 3.135V VOL@MIN = 1 V VOL@MAX =0.4V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.4
TYP
MAX 24 24 0.4 -46
UNITS V V mA mA ns ns % ps ns
Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Propagation delay SDRAM_IN to SDRAM
1
-54 54 53 0.4 0.4 45 1.1 0.75 50 30 2.95 1.6 1.6 55 250 4
1 1 1
dt5
tsk5
tpdel5
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Frequency FO4 VO = VDD*(0.5) Output Impedance RDSP41 1 IOH = -1 mA Output High Voltage VOH4 1 IOL = 1 mA Output Low Voltage VOL4 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH41 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL4 VOL = 0.4 V, VOH = 2.4 V Rise Time tr41 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf4 1 Duty Cycle VT = 1.5 V dt1 tjcyc-cyc41 VT = 1.5 V Jitter, cycle-to-cycle
1
MIN 20 2.4 -29 29 1 1 45
TYP 14.318
MAX 60 0.4 -23 27 4 4 56 550
1.85 1.95 55.7 365
UNITS MHz V V mA mA ns ns % ps
Guaranteed by design, not 100% tested in production.
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ICS950602
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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Power Down Waveform
0ns 1 25ns 50ns 2
VCO Internal CPU 100MHz 3.3V 66MHz PCI 33MHz APIC 16.7MHz PD# SDRAM 100MHz REF 14.318MHZ 48MHZ
Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
0469B--12/18/02
14
Integrated Circuit Systems, Inc.
ICS950602
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950602yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device
0469B--12/18/02
15
Integrated Circuit Systems, Inc.
ICS950602
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D
a
A A1 A2 b c D E E1 e L N aaa VARIATIONS N
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 -0.10 -.004
A2 A1
A
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
-Ce
b SEATING PLANE
48
10-0039
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil) (240 mil)
Ordering Information
ICS950602yGT
Example:
ICS XXXX y G - T
Designation for tape and reel packaging Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device
0469B--12/18/02
16

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